1. Field of the Invention
The present invention relates to a semiconductor device having a trench structure and a method for fabricating the same.
2. Description of Related Art
Some power MOS FETs (Metal-Oxide-Semiconductor Field Effect Transistor) have a construction wherein a gate electrode is embedded in a trench formed in a semiconductor substrate (a thin film overlaid on the semiconductor substrate). Conventionally, polysilicon rendered conductive by introducing impurities therein has been used as a material for forming the gate electrode.
However, the gate electrode formed of polysilicon has such a high resistance that the switching operations of the MOS FET cannot be increased in speed. In this connection, efforts have been made to achieve high-speed switching operations of the MOS FET by reducing the resistance of the gate electrode.
FIG. 5 is a sectional view illustrating a construction of a conventional semiconductor device formed with the MOS FET having a trench structure. Such a semiconductor device is disclosed in, for example, U.S. Pat. No. 6,274,905.
The semiconductor device 50 includes an N− region 51 formed on a semiconductor substrate, and a semiconductor layer 52 overlaid on the N− region 51. The semiconductor device 50 is further formed with a plurality of trenches 53 penetrating through the semiconductor layer 52 to reach a surface of the N− region 51.
An N+ region 54 is formed at a surface of the semiconductor layer 52 at an edge of the trench 53. A P+ region 55 is formed between the N+ regions 54 formed at the individual edges of two adjoining trenches 53. The remainder of the semiconductor layer 52 (a portion exclusive of the N+ region 54 and the P+ region 55) defines a P− region 56. The trench 53 penetrates through the P− region 56.
An insulating (dielectric) layer 57 such as formed of silicon oxide is formed along an inside wall of the trench 53. A gate electrode 62 is disposed in the trench 53. The gate electrode 62 includes a polysilicon layer (buffer layer) 58, a low-resistance layer (a core of high conductivity) 59, and a polycide layer 63 formed between the polysilicon layer 58 and the low-resistance layer 59. The polysilicon layer 58 is rendered conductive by introducing impurities therein. The low-resistance layer 59 contains therein a metal having a high melting point (such as tungsten (W)). In a case where the low-resistance layer 59 contains tungsten, the polycide layer 63 contains therein tungsten polycide (WSi).
The polysilicon layer 58 is formed on the insulating layer 57 in a manner to conform to the inside wall of the trench 53. The remainder in the trench 53 (a further inward region) is filled with the low-resistance layer 59. With respect to a depthwise direction of the trench 53, the low-resistance layer 59 is formed in a depth range substantially corresponding to a depth in which the P− region 56 is formed. Thus, the low-resistance layer 59 is in opposing relation with the P− region 56 with the insulating layer 57 and the polysilicon layer 58 interposed therebetween.
Formed on the semiconductor layer 52 is an electrode film (metallic source layer) 60 electrically connected with the N+ region 54 and the P+ region 55. Formed over the trench 53 is an insulating (dielectric) layer 61, which electrically isolates the polysilicon layer 58 and the low-resistance layer 59 from the electrode film 60.
A proper voltage is applied between the N− region 51 and the electrode film 60, and the gate electrode 62 is set at a proper potential, whereby a channel is formed in the P− region 56 in the vicinity of an interface with the insulating layer 57 so that an electric current is allowed to flow between the N− region 51 and the electrode film 60.
The gate electrode 62 of this semiconductor device 50 is reduced in resistance as compared with a gate electrode consisting of polysilicon. Hence, the semiconductor device 50 has achieved high-speed switching operations.
However, in a case where a metal is used as a material for forming the gate electrode 62, the semiconductor device 50 encounters a great shift of drive voltage compared with the case where the gate electrode consists of polysilicon. The drive voltage of the semiconductor device 50 depends upon a threshold voltage VT=VFB+2ψB+(2εsqNA(2ψB))1/2/C0=(φ−Qf/C0)+2ψB+(4εsqNAψB)1/2/C0.
In the above expression, VFB represents a flat-band voltage; ψB represents an electrostatic potential at an interior (bulk) of the semiconductor device (the P− region 56); εs represents a dielectric constant of the semiconductor portion (the P− region 56); q represents an elementary electric charge; NA represents a concentration of acceptor impurities; C0 represents a per-unit-area capacitance of the insulating layer 57; φ represents a difference between a work function of the gate electrode 62 (the polysilicon layer 58) and a work function of the semiconductor portion (the P− region 56) (hereinafter, simply referred to as “work function difference”), the gate electrode opposing the semiconductor portion via the insulating layer 57; and Qf represents a fixed charge in the insulating layer 57. That is, the threshold voltage varies depending upon the work function difference φ.
Since not only the polysilicon layer 58 but also the low-resistance layer 59 containing the metal (having the high melting-point) are in opposing relation with the P− region 56, the work function difference φ is greatly shifted compared with that of the semiconductor device wherein only the polysilicon layer 58 opposes the P− region 56 via the insulating layer 57. Accordingly, there is a great difference between the threshold voltage VT of the common MOS FET employing the gate electrode consisting of polysilicon and that of the semiconductor device 50 employing the gate electrode mainly consisting of metal. Hence, the drive voltage differs greatly between the common MOS FET and the semiconductor device 50.
In other words, the semiconductor device 50 must be drastically changed in design if the semiconductor device employing the gate electrode 62 essentially consisting of metal is to retain unchanged device characteristics such as the drive voltage.
More recently, the patterns have been miniaturized even further, so that the trench 53 may sometimes be formed in depth on the order of 1 μm to 3 μm and in width on the order of 0.3 μm to 0.5 μm. An expensive apparatus must be used in order to embed the metal favorably (densely) in the trench 53 having such a high aspect ratio.